1) Field of the Invention
The present invention relates to a ferroelectric memory that uses polarization of a ferroelectric capacitor for storing data in the memory.
2) Description of the Related Art
A memory for storing data through the use of polarization of a ferroelectric capacitor is known in the prior art and is called a ferroelectric memory. Using a ferroelectric substance achieves a semiconductor memory having such characteristics as nonvolatility and random accessiblity.
A principle of the ferroelectric memory device is disclosed in articles such as “Low Power-consumption High-speed LSI Technology,” Realize Incorporated, Jan. 31, 1998, pp.231-250. A circuitry of the ferroelectric memory is disclosed in Japanese Patent Laid-open Publication Kokai No.2002-15562.
As disclosed in the Japanese Patent Laid-open No.2002-15562, the ferroelectric memory device includes a memory cell array. The memory cell array includes one or a plurality of memory cell blocks. Each memory cell block includes a plurality of ferroelectric memory cells arranged in the form of a matrix, a plurality of bit lines, a plurality of word lines and a plurality of plate lines.
The ferroelectric memory cell includes one or two transistors and one or two ferroelectric capacitors. A ferroelectric memory cell including only one transistor and only one ferroelectric capacitor is called a 1T1C type memory cell. A ferroelectric memory cell including two transistors and two ferroelectric capacitors is called a 2T2C type memory cell.
Bit lines are provided along a row direction of the ferroelectric memory cells. A drain of each transistor within the ferroelectric memory cell is commonly connected to a corresponding bit line.
Word lines and plate lines are provided along a column direction of the ferroelectric memory cells. The word line is connected to a gate of a corresponding transistor. The plate line is connected to a source of a corresponding transistor via a ferroelectric capacitor.
When the data is read, a reading potential is applied to the selected word line and the selected plate line. As a result, the transistor is turned on, thereby the memory data is output to the bit line. A value of the memory data varies depending on a polarization direction of the ferroelectric capacitor.
Owing to the reading of the data from the ferroelectric memory, the memory data is destroyed. Memory data having the same value is therefore rewritten every time the data is read from the ferroelectric memory cell.
As described above, the word lines and the plate lines are both provided in a column direction. Therefore, the data are simultaneously read from all the ferroelectric memory cells which are connected to the same word line and the same plate line when reading the data. For example, if eight ferroelectric memory cells are connected to the same word line and the same plate line, it is impossible to read data from only four ferroelectric memory cells out of these eight ferroelectric memory cells. When the reading of only four memory cells is required, these eight data are read first, thereafter, only the four necessary data are output from the memory cell array.
As is widely known, characteristics of the ferroelectric capacitor deteriorate depending on the number of times for accessing the data. The ferroelectric capacitor no longer stores the data if such deterioration develops to a certain extent. Because of this, the ferroelectric memory has the disadvantage of a short life time.
In addition, the ferroelectric memory in the prior art is configured to simultaneously read unnecessary data as described above. Furthermore, rewriting after reading must be carried out for such unnecessary data. This rewriting substantially decreases the lifetime of the ferroelectric memory.
For example, in the aforementioned case, that is, in the case of the ferroelectric memory which requires accessing the eight ferroelectric memory cells for reading only four bits data, the number of times for accessing the cells to read the necessary data is equal to the number of times for accessing the cells to read the unnecessary data. Consequently, the lifetime of the ferroelectric memory is substantially decreased by half.
When the maximum number of accessible times of the ferroelectric capacitor is 1010, an average value of the maximum number of accessible times will be 5×109 for the ferroelectric memory which requires accessing the eight ferroelectric memory cells for reading the four bits data.
At the end of the life of the ferroelectric memory, a read data value is liable to be different from the written value, which impairs the reliability of the read data.
In order to decrease the number of unnecessary data accessing operations to the ferroelectric memory cell, it is effective to reduce the number of memory cells per unit memory cell block. Specifically, downsizing of the memory cell block reduces the number of memory cells which are connected to the same word line and the same plate line. Accordingly, the number of unnecessary data accesses can be decreased. However, downsizing of the memory cell block will increase the number of word lines and plate lines, thereby a circuit size which controls the word lines and plate lines is expanded.